FIG. 1 illustrates a typical phase locked loop (PLL) 10. The PLL comprises in order: a reference oscillator 12, a reference counter 14, a phase detector 16, a loop filter 18, a voltage controlled oscillator 20, and a feedback loop 22 from the VCO 20 through a loop counter 24 to the phase detector 16.
Reference oscillator supplies a reference frequency signal 21, having a frequency Fref, to the reference counter 14. The reference counter operates as a divider and produces an output pulse when it has counted M input pulses of the reference frequency signal 21. The value of M can be varied via an input control signal 23. Thus the first counter produces a reduced frequency input signal 25 which has a frequency 1/M Fref.
The phase detector 16 receives the reduced frequency input signal 25 at one input and a reduced frequency output signal 27 at the other input. The output signal 29 from the phase detector passes through the loop filter 18 to provide an input voltage signal 31 to the VCO 20. The loop filter is generally a series combination of a resistor and a capacitor connected from a node, in the connection between the phase detector 16 and the VCO 20, to ground. The loop filter may alternatively include a second capacitor connected in parallel with the resistor, or in parallel with the resistor-capacitor combination. The VCO 20 converts the input voltage signal 31 to an oscillating output signal 33 at frequency Fout.
The oscillating output signal 33 is fed to loop 22, where it is input to the loop counter 24. The loop counter 24 operates as a divider producing an output pulse when it has counted N input pulses of the oscillating output signal 33. The value of N can be varied via an input control signal 35. Thus the second counter provides as a second input to the phase detector 16, a reduced frequency output signal 27 which has a frequency 1/N Fout.
When the reduced frequency output signal 27 lags the reduced frequency input signal 25, the phase detector 16 sources current to the loop filter 18 and the voltage input to the VCO 20 rises. The VCO 20 increases the frequency Fout of the oscillating output signal 33 and the reduced frequency output signal, which reduces the lag.
When the reduced frequency output signal 27 leads the reduced frequency input signal 25, the phase detector 16 sinks current from the loop filter 18 and the voltage input to the VCO 20 drops. The VCO 20 decreases the frequency Fout of the oscillating output signal 33 and the reduced frequency output signal, which reduces the lead.
Consequently, the loop moves towards ‘lock’ at which Fout=Fref*N/M
Such phase locked loops suffer from a number of problems. One problem is a long settling time after a change in frequency which may make it unsuitable for modern multi-slot communication systems, in which changes in frequency occur at higher rates than in non multi-slot communication systems. For example in General Packet Radio System (GPRS) the PLL at a terminal needs to change frequency every slot.
Another problem is the PLL's susceptibility to phase noise as the sensitivity of the VCO increases. The current trend is towards using low operational voltages and VCO sensitivity must be increased if the same frequency range of output is required from lower operational voltages (e.g. 3V and below). The sensitivity of the VCO may also be increased to accommodate frequency overshoot during a frequency change.
It would be desirable to provide an improved phase locked loop.